The latest data acquisition system running at the Jicamarca Radio Observatory (JRO) for the main radar has been used for more than seven years now. Although there are no major inconveniences on the performance, there have been some problems with internal interference which are related to the PCB design that uses old discrete components. A new design is proposed for the digital receivers, giving it more lifetime and flexibility for future modifications. The JESD204B protocol is ideal for radar applications, a JESD204B ADC together with an FPGA was proposed for the new design, making it capable of a wider bandwidth which could adapt the system to an SDR device in the future with the proper software. This paper will present the new PCB design, the IP cores implemented for the FPGA and some preliminary tests with development boards.